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GS74116TP/J/U SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features
* Fast access time: 8, 10, 12, 15ns * CMOS low power operation: 170/145/130/110 mA at min.cycle time. * Single 3.3V 0.3V power supply * All inputs and outputs are TTL compatible * Byte control * Fully static operation * Industrial Temperature Option: -40 to 85C * Package line up J: 400mil, 44 pin SOJ package TP: 400mil, 44 pin TSOP Type II package U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
256K x 16 4Mb Asynchronous SRAM
SOJ 256K x 16 Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
8, 10, 12, 15ns 3.3V VDD Center VDD & VSS
Top view
44 pin SOJ
Description
The GS74116 is a high speed CMOS static RAM organized as 262,144-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS74116 is available in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II packages.
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A17
Pin Descriptions Symbol
A0 to A17 DQ1 to DQ16 CE LB UB WE OE VDD VSS NC
Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3V power supply Ground No connect
Fine Pitch BGA 256K x 16 Bump Configuration
1 2 3 4 5 6
A B C D E F G H
LB DQ16
OE UB
A0 A3 A5 A17 NC A8 A10 A13
A1 A4 A6 A7 A16 A9 A11 A14
A2 CE DQ2 DQ4 DQ5 DQ7 WE A15
NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC
DQ14 DQ15 VSS VDD DQ13 DQ12
DQ11 DQ10 DQ9 NC NC A12
7.2x11.65mm 0.75mm Bump Pitch Top View Rev: 2.02 3/2000 1/14 (c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
TSOP-II 256K x 16 Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A17
Top view
44 pin TSOP II
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A17 CE WE Control OE _____ UB LB _____
Column Decoder
I/O Buffer
DQ1
DQ16
Rev: 2.02 3/2000
2/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z
DQ9 to DQ16
Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
IDD
L L
H X
H X
X H
Note: X: "H" or "L"
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD+0.5 ( 4.6V max.) -0.5 to VDD+0.5 ( 4.6V max.) 0.7 -55 to 150
Unit
V V V W
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 2.02 3/2000
3/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U Recommended Operating Conditions
Parameter
Supply Voltage for -10/12/15 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VDD VIH VIL TAc TAI
Min
3.0 3.135 2.0 -0.3 0 -40
Typ
3.3 3.3 -
Max
3.6 3.6 VDD+0.3 0.8 70 85
Unit
V V V V
o
C C
o
Note: 1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns. 2. Input undershoot voltage should be greater than -2V and not exceed 20ns.
Capacitance
Parameter
Input Capacitance Output Capacitance
Symbol
CIN COUT
Test Condition
VIN=0V VOUT=0V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA=25C, f=1MHz 2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL ILO VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = - 4mA ILO = + 4mA
Min
-1uA -1uA 2.4
Max
1uA 1uA
0.4V
Rev: 2.02 3/2000
4/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Power Supply Currents Parameter Symbol Test Conditions
CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2V All other inputs VDD - 0.2V or 0.2V
0 to 70C 8ns 10ns 12ns 15ns 10ns
-40 to 85C 12ns 15ns
Operating Supply Current
IDD
170mA
145mA
130mA
110mA
155mA
140mA
120mA
Standby Current
ISB1
70mA
65mA
60mA
55mA
75mA
70mA
65mA
Standby Current
ISB2
30mA
40mA
AC Test Conditions
Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH=2.4V VIL=0.4V tr=1V/ns tf=1V/ns 1.4V 1.4V Fig. 1& 2
Output Load 1
DQ 50 VT=1.4V 30pF1
Output Load 2
3.3V DQ 5pF1 589 434
Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Rev: 2.02 3/2000
5/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U AC Characteristics
Read Cycle Parameter
Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Byte disable to output in High Z (UB, LB)
Symbol
tRC tAA tAC tAB tOE tOH tLZ* tOLZ* tBLZ* tHZ* tOHZ* tBHZ*
-8 Min
8 --------3 3 0 0 -------
-10 Max
--8 8 3.5 3.5 --------4 3.5 3.5
-12 Min
12 --------3 3 0 0 -------
-15 Min
15 --------3 3 0 0 -------
Min
10 --------3 3 0 0 -------
Max
--10 10 4 4 --------5 4 4
Max
--12 12 5 5 --------6 5 5
Max
--15 15 6 6 --------7 6 6
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC Address tAA tOH Data Out Previous Data Data valid
Rev: 2.02 3/2000
6/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ UB, LB OE tBLZ tOE Data Out tOLZ High impedance tAB tBHZ tOHZ Data valid tHZ
Write Cycle Parameter
Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z
Symbol
tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ*
-8 Min
8 5.5 5.5 5.5 4 0 5.5 0 0 0 3 ---
-10 Max
----------------------3.5
-12 Min
12 8 8 8 6 0 8 0 0 0 3 ---
-15 Min
15 10 10 10 7 0 10 0 0 0 3 ---
Min
10 7 7 7 5 0 7 0 0 0 3 ---
Max
----------------------4
Max
----------------------5
Max
----------------------6
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested
Rev: 2.02 3/2000
7/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Write Cycle 1: WE control
tWC Address tAW OE tCW CE tBW UB, LB tAS WE tDW Data In tWHZ Data Out tDH Data valid tWLZ High impedance tWP tWR
Write Cycle 2: CE control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 2.02 3/2000
8/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Write Cycle 3: UB, LB control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 2.02 3/2000
9/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
44 Pin, 400 mil SOJ Symbol
A A1 A2 HE GE E B B1 1 e 22
A
D 44 23
L c
Dimension in inch min nom max
0.025 0.018 0.008 0.148 -
Dimension in mm min nom max
0.635 2.667 0.660 28.44 9.144 2.083 0o 2.794 0.457 0.711 0.203 28.58 1.27 9.398 2.210 3.759 2.921 0.813 28.70 9.652 2.70 0.102 7o
0.105 0.110 0.115 0.026 0.028 0.032 1.120 1.125 1.130 0.05 -
c D E e
0.395 0.400 0.405 10.033 10.160 10.287 0.435 0.440 0.445 11.049 11.176 11.303 0.360 0.370 0.380 0.082 0.087 0.106 0o 0.004 7o
A
A2
A1
y
B B1 Detail A
HE Q GE L y Q
Note: 1. Dimension D& E do not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion
Rev: 2.02 3/2000
10/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
44 Pin, 400 mil TSOP-II Dimension in inch Dimension in mm Symbol min nom max min nom max
A A1 HE
A
44
D
23
c
0.002 0.01 -
-
0.047 -
0.05 0.95 0.25 -
1.00 0.35 0.15
1.20 1.05 0.45 -
E
A2 B c D E e HE L
0.037 0.039 0.041 0.014 0.018 0.006 -
1 A2
e
22 B
0.721 0.725 0.729 18.31 18.41 18.51 0.396 0.400 0.404 10.06 10.16 10.26 0.031 0.40 0
o
0.80 0.50 0.80 -
0.60 0.10 5o
A
0.455 0.463 0.471 11.56 11.76 11.96 0.016 0.020 0.024 0
o
A1
y L1 L
L1 y Q
0.031 -
0.004 5
o
Detail A
Q
Note: 1. Dimension D& E do not include interlead flash 2. Dimension B does not include dambar protrusion / intrusion 3. Controlling dimension: mm
Rev: 2.02 3/2000
11/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U 7.2mmx11.65mm FP-BGA D
Symbol A A1 Unit: mm 1.10 0.10 * 0.22 0.05
b
0.35
0.36(TYP) 11.65 0.10 5.25 7.20 0.10 3.75 0.75(TYP) 0.10
E
Pin A1 Index
c D D1 E E1
Top View
e
A
c
aaa
A1
Pin A1 Index
Side View
ABCDEFGH
aaa
b Solder Ball
1 2 3 4 5 6
e
E1
e D1
Bottom View
Rev: 2.02 3/2000
12/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Ordering Information Part Number*
GS74116TP-8 GS74116TP-10 GS74116TP-12 GS74116TP-15 GS74116TP-8I GS74116TP-10I GS74116TP-12I GS74116TP-15I GS74116J-8 GS74116J-10 GS74116J-12 GS74116J-15 GS74116J-8I GS74116J-10I GS74116J-12I GS74116J-15I GS74116U-8 GS74116U-10 GS74116U-12 GS74116U-15 GS74116U-8I GS74116U-10I GS74116U-12I GS74116U-15I
Package
400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA
Access Time
8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns
Temp. Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Status
*
Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example: GS74116TP-10T
Rev: 2.02 3/2000
13/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U Revision History
Rev. Code: Old; New
Rev1.03c 3/1999; 1.04d 6/1999
Types of Changes Page #/Revisions/Reason Format or Content
Format/Typos Content Format/Typos Document/Changed format of subscripts on pins to small caps. 13/Changed Tape and Reel Note at end of Ordering info./Enhancement None 1. 2. 3. 1. 2. 1. Added Fine Pitch BGA package to datasheet. 10/Added Dimension "D" to SOJ package diagram/Was missing 11/Added Dimension "D" to TSOP package diagram/Was missing GSI Logo Changed Pin A17 from 3E to 3D.
1.04d 6/1999; 2.00 8/1999
Content Format/Content Content
GS741Rev2.01KRev 21 2/2000L GS74116 Rev2.01 2/2000L; Rev 2.02 3/2000N
Rev: 2.02 3/2000
14/14
(c) 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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